The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 1990
Filed:
Jul. 11, 1989
Gerard A Kreifels, Citrus Heights, CA (US);
Other;
Abstract
An almost full flag for a FIFO includes first and second counters for determining the proximity of the Read and Write pointers in the FIFO. A compare circuit is provided for comparing the output of the counters to determine when the count values are separated by a predetermined value. When the separation is equal to the predetermined value, the output of the comparitor goes low. A half flag is set when a Write operation occurs and the difference value between the Read and Write pointers increases. The set operation is performed in response to the presence of the compare signal at a low logic state at the time that the Write operation occurs, thus eliminating any delays in generating a transition in the compare circuit. The flag is reset when the compare signal is at the low logic state. Blanking circuitry is provided for blanking the reset operation when a Read operation occurs and the output of the comparator makes a transition from the first logic state to the second logic state. The blanking operation occurs for a predetermined duration of time to allow the counter to settle before performing the reset operation.