The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 1989

Filed:

Mar. 28, 1986
Applicant:
Inventors:

David J Lilja, Sunnyvale, CA (US);

A Richard Zacher, Los Gatos, CA (US);

Steven W Wierenga, Sunnyvale, CA (US);

Assignee:

Tandem Computers Incorporated, Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
364200 ; 364241 ; 3642411 ; 3642283 ; 3642715 ; 3642292 ; 3642408 ; 3642409 ; 3642401 ;
Abstract

A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.


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