Vector pattern processing circuit for bit map display system

Abstract

A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.