The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 1989
Filed:
Sep. 09, 1988
Joseph P Farina, Southwick, MA (US);
United Technologies Corporation, Hartford, CT (US);
Abstract
A sine wave locked in phase and frequency to a carrier having a high second harmonic content, carrying information on the magnitude of a parameter, is applied to an open loop operational amplifier which provides a trapezoidal waveform to a high speed, differential transistor pair which provides a pair of squarewave signals whose duty cycles are regulated by varying the threshold at which the differential pair switches. The squarewaves may be used as a second-harmonic-free demodualting signal. The fundamental premise is that if the amplitude levels of the squarewave levels of the squarewave are known to a high degree of accuracy, and they are equal in the positive and negative directions, then the average value is zero only for a 50% duty cycle. A current regulator generates a selected current to a constant value with a high gain amplifier. This current is switched from one side to the other of the differential pair by the trapezoidal waveform. The voltage excursions may be controlled in equal amounts above and below zero by selecting the resistive values in the collector circuits of the differential pair to be of a magnitude which will accomplish that end. The average value of the resulting squarewave is regulated to zero by integrating the voltage at the output of one of the collectors of the differential pair and varying the threshold at the base of the other transistor to obtain a 50% duty cycle.