Error checking and correcting for read-modified-write operations

Abstract

Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle. During this RMW operation, the ECC logic detects and corrects a single bit error (if one exists) concurrent with modification of the word and calculation of new ECC bits. The corrected word is then modified by the data bits from the CPU, new ECC bits are calculated and the latter modified word and ECC bits are entered into the storage unit rather than the former word which contained a single bit error. If no error exists, a short RMW cycle is used; if a single bit error exists a longer RMW cycle is used.