The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 1989
Filed:
Jun. 14, 1988
Akira Ishizuka, Tokyo, JP;
Toshihiko Nakamura, Yamanashi, JP;
NEC Corporation, Tokyo, JP;
Abstract
A summing circuit (20) is for summing up zeroth through n-th input data signals A(0) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(0) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(0) to A(n) into a preprocessed signal which is (n+1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(0) to A(n) is given by an equation: ##EQU1## where a(d) represents a d-th coefficient having one of logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value. Each of the zeroth through the n-th input data signals A(0) to A(n) may be given by another equation: ##EQU2## where p(d)'s represent zeroth through n-th discrete integers.