Semiconductor memory device using partial decoders for redundancy

Abstract

In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.