The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 1989
Filed:
May. 31, 1988
Applicant:
Inventors:
Nirmal S Virdee, Phoenix, AZ (US);
Hamid R Baradaran, Glendale, AZ (US);
Assignee:
Siemens Transmission Systems, Inc., Phoenix, AZ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H04L / ;
U.S. Cl.
CPC ...
375106 ; 307265 ; 328 58 ; 375118 ;
Abstract
A retiming circuit is provided which accurately converts half-width dual rail data with up to one unit interval of jitter with respect to the data clock, into full-width data. The circuit is comprised of D-flip-flops and associated logic elements which capture and hold a data pulse until the captured data pulse can be accurately transferred to the next circuit stage by a positive clock transition.
Virdee, Nirmal. (1989). Jitter tolerant circuit for dual rail data (U.S. Patent No. 4879730). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4879730
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile