Semiconductor memory device with a data clear circuit

Abstract

A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.