A gaas register file having a plurality of latches

Abstract

A GaAs register file for storing of digital data is configured with a plurality of latches having a data terminal and an enable terminal connected to a write enable circuit. The wire enable circuit provides a write enable strobe signal to enable the latch during the loading of data into the plurality of latches. The write enable circuit has an enable input circuit, a clock input circuit and two combining circuits. The enable input circuit receives an enable signal from an address decode logic and provides a time delay to the enable signal. The clock input circuit receives a clock signal and delays the clock signal signal. The delayed clock signal and enable signal are combined to obtained a combination signal. A second clock delay is provided by plurality of series connected GaAs gates which defines the width of the write enable puse. The second clock delayed signal is ANDED with the combination signal to obtained the write enable strobe signal.