The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 1989
Filed:
Jan. 26, 1988
Questech Limited, Wokingham, GB;
Abstract
In a method of processing a video signal to provide digital video effects, an image signal is provided with an accompanying reference signal or Z-axis signal representative of the instantaneous distance of the scanning point of the video raster from an imaginary plane to be depicted as containing said information, taken in a direction perpendicular to the image screen. This reference signal may then be utilized to produce a variety of effects. For example a circuit for superimposing sets of image information to give the impression of an overlap in three dimensional space may comprise an order sorting circuit (1) having inputs (2,3,4) for sets of signals comprising picture information (P) a key signal (K) and a Z-axis signal (Z). At outputs (5,6,7) of the circuit the sets of signals are sorted into order of priority dependent on the magnitude of the Z-axis signal (Z). The picture signals (P) are mixed by multipliers (25,26,27) and a summer (28) to provide a composite picture signal in which the mixing of the components is determined by the multiplication factors of the multipliers (25,26,27). These factors are derived from the key signals having corresponding orders of priority, the key signals of lower order of priority being correspondingly attenuated by cascaded attenuators (12,13,14) coupled between lower order outputs of the sorting circuit (1) and a weighting circuit (11) for controlling the multipliers (25,26,27).