The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 1989
Filed:
Aug. 31, 1988
Applicant:
Inventor:
Wayne G Fisher, Allen, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437225 ; 437974 ; 437946 ; 156626 ; 156636 ; 156645 ; 511311 ;
Abstract
A process for planarizing the surface of a semiconductor wafer, after the wafer has been processed to form nonplanar topography layers on the blank, polished wafer, by mechanically removing material from this surface by abrasion until a desired planarity is attained. The mechanical planarization prevents step coverage problems encountered in further processing, avoids multiple step prior art planarizing methods, and can be effectively controlled by several simple methods.
Fisher, Wayne. (1989). Integrated circuit planarization by mechanical polishing (U.S. Patent No. 4879258). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4879258
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile