The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1989
Filed:
Oct. 20, 1987
Katsuhiro Sasaki, Tokyo, JP;
Seiji Fukuda, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A digital signal transmission system includes a transmit terminal which as an input interface circuit, a synchronous conversion circuit, a synchronous conversion circuit, a parity check circuit, a multiplex circuit for multiplexing a synchronized input signal with at least a parity check signal, a transmitter and antenna. A fault detector circuit of the transmit terminal detects faults in the input interface stage. The outputs of the fault detector circuit and the parity check circuit are input to a parity check signal output circuit which operates to invert the logical state of the output of the parity check circuit when a fault is detected. A digital signal reception system includes a receive terminal, which has a demultiplex circuit, a frame synchronization circuit, a parity check circuit, a synchronous conversion circuit, an output inface circuit, a receiver and antenna. The transmitted parity check signal is recovered from the demultiplex circuit. The receive terminal parity check circuit determines the parity signal from the received signal. A receive terminal parity check signal comparison circuit compares the determined parity signal with the recovered parity check signal. A fault in the transmit terminal input stage will be recognized at the receive terminal as a non-coincidence output from the comparison circuit.