The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 1989

Filed:

Jun. 10, 1988
Applicant:
Inventor:

James L Paterson, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437 52 ;
Abstract

The specification discloses a floating gate read only memory formed in an array of rows (15) and columns (17) of memory cells (10). A conductivity-type determining layer (24) is formed over a face of a semiconductor body (30). An oxide layer (32) is formed over layer (24) and spaced apart elongated trenches (44) are formed through the layers (32) and (24) to form columns (17) of impurity layers. A first gate insulating layer (32a) is formed over the trenches (44). Discrete regions of polycrystalline silicon (34) are formed over spaced apart locations of the trenches (44) to form floating gates. A second gate insulating layer (36) is formed over the floating gates. A pattern of spaced apart parallel strips (40) are formed overlying the floating gates and normal to the columns (17) to form the rows (15) of memory cells.


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