Method of making asymmetrically optimized cmos field effect transistors

Abstract

A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.