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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4874476 B1

PDFFull Text
Date of Patent:
Oct. 17, 1989

Filed:

Oct. 05, 1988

Fixture for plating tall contact bumps on integrated circuit

Applicant:
Inventors:

Roger J Stierman, Richardson, TX (US);

Archie N McCauley, Little Elm, TX (US);

Robert C Zart, Dallas, TX (US);

Assignee:

Texas Instruments Incorporated, Dallas, TX (US);

Attorneys:

Honeycutt; Gary C.

Sharp; Melvin

Merrett; Rhys

Primary Examiner:

T M Tufariello

Int. Cl.
CPC ...
C25D / ;
U.S. Cl.
CPC ...
204 15 ;
Abstract

A method of plating bumps on metallization on the face of a wafer, including the steps of placing the wafer in a transportable fixture wherein cathode needles press against the face of the wafer to make electrical contact and to force the back side of the wafer against a sealing member to prevent the plating bath from contacting the back side. The fixture with the wafer therein is placed in a clean up or presoak bath and is then transported to a plating bath without an operator having to touch the wafer.

Find Patent Forward Citations

Stierman, Roger. (1989). Fixture for plating tall contact bumps on integrated circuit (U.S. Patent No. 4874476). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4874476

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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