Scientific processor to support a host processor referencing common

Abstract

An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry. A plurality of vector manipulating pipelines for performing instruction functions of vector addition, vector multiplication and vector move is described wherein the pipelined functions can occur simultaneously, and each pipeline is capable of providing resultant operand pairs at a rate approximately equal to the reference cycle of the High Performance Storage Unit.