Monolithic semi-custom ic having standard lsi sections and coupling gate

Abstract

In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.