The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 1989
Filed:
Sep. 06, 1988
Eric Neely, Mesa, AZ (US);
Michael Wells, Chandler, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.