The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 1989
Filed:
Nov. 15, 1988
Masashi Arai, Gunma, JP;
Ryuichi Ogawa, Gunma, JP;
Sanyo Electric Co., Ltd., , JP;
Abstract
A PLL circuit comprises a variable frequency divider (7) for frequency-dividing a signal having a reference frequency f.sub.1 with a frequency dividing ratio n.sub.1 or n.sub.2, a fixed frequency divider (8) for further frequency-dividing an output of the variable frequency divider with a frequency dividing ratio n.sub.0, to generate a first output signal and a second output signal which is out of phase by 90.degree. from the first output signal, multiplier (10) for multiplying an input signal by the second output signal, a comparator (11) for comparing an output of the multiplier with a predetermined reference voltage, and a D-type flip-flop (12) receiving as a D input an output of the comparator and receiving as a clock input the first output signal, an output of the D-type flip-flop (12) being applied to the variable frequency divider (7). When the second output signal leads the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an 'L' level, so that the large frequency dividing ratio n.sub.2 is selected. On the other hand, when the second output signal lags the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an 'H' level, so that the small frequency dividing ratio n.sub.1 is selected.