The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 1989
Filed:
Oct. 14, 1986
Applicant:
Inventor:
Brian J Van Ness, Aurora, CO (US);
Assignee:
Monolithic Systems Corp., Englewood, CO (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365208 ; 365 63 ; 365214 ;
Abstract
A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.
Van Ness, Brian. (1989). Memory chip array with inverting and non-inverting address drivers (U.S. Patent No. 4870619). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4870619
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile