The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 1989

Filed:

Sep. 23, 1988
Applicant:
Inventors:

Hiroshi Sekiya, Kamakura, JP;

Ikuya Arai, Yokohama, JP;

Toshinori Murata, Yokohama, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ; H04N / ;
U.S. Cl.
CPC ...
358158 ; 358242 ; 315387 ;
Abstract

In a television receiver including a digital circuit processing an input video signal in a digital mode, a clock generating circuit applies a system clock signal to the digital circuit, and comprises a phase comparator to which a horizontal synchronizing signal is applied, a low-pass filter connected to the phase comparator, a voltage controlled oscillator connected to the low-pass filter to generate the system clock signal, a first frequency divider dividing the frequency of the system clock signal generated from the voltage controlled oscillator to generate a horizontal deflection drive pulse signal, and a second frequency divider connected to the phase comparator. The phase comparator, the low-pass filter, the voltage controlled oscillator, the first frequency divider and the second frequency divider constitute a single PLL circuit, and the system clock signal and the horizontal deflection drive pulse signal are respectively generated from the PLL circuit.


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