The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 1989
Filed:
Apr. 15, 1988
Peter F Corbett, Princeton, NJ (US);
General Electric Company, Schenectady, NY (US);
Abstract
A circuit for supplying safe logic zero and logic one signals to hardwired inputs of CMOS ICs comprises, at most, three field effect transistors, none of which have gates connected to either drain voltage V.sub.dd or source voltage V.sub.ss. The circuit has no external inputs and has two outputs, logic zero and logic one. The circuit has only one stable operating point and moves to this operating point from any initial condition. The circuit is safe and can enhance the reliability of ICs as it provides the same noise protection from voltages V.sub.ss and V.sub.dd for nodes connected to its output that an inverter provides for nodes connected to its output.