The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 1989

Filed:

Aug. 15, 1985
Applicant:
Inventors:

John W Kish, Roswell, GA (US);

John S Alcorn, Symrna, GA (US);

David B Burleson, Snellville, GA (US);

Assignee:

Lanier Business Products, Inc., Atlanta, GA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364200 ; 364228 ; 3642281 ; 3642461 ; 3642563 ;
Abstract

An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided for maintaining a memory map, which translates addresses in the main processing unit address space into physical memory addressess of a primary memory. A network interface allows pages or segments of data from a secondary memory connected to a communications network to be transferred into the primary memory in a manner transparent to the operation of the main processing unit. A direct memory access (DMA) circuit transfer the header portion of a network-transferred page of data into a separate auxiliary addressable memory for storage of network overhead information, while the useful data portions of the page are stored directly in locations in the primary addressable memory. A requested page of data is then placed directly in a desired location in primary memory without the need for moving or retransferring the data within the primary memory to strip off network header information after a DMA transfer. The system is responsive to detect and correct a page fault condition prior to execution of the main processing unit instruction which generated the page fault, which obviates reexecution of instructions or correction of instruction execution results by the main processing unit.


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