Self-correcting digitally controlled timing circuit

Abstract

A digitally controlled timing circuit for providing an output pulse signal precisely delayed with respect to an input signal irrespective of the time of occurrence of a system clock, but which uses the precision of the system clock to self-correct any inaccuracy in the delay includes a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between an input terminal, to which an input terminal is applied, and an output terminal, from which a delayed output signal is to be derived. Coupled to the input terminal and the plurality of delay elements is a toggled flip-flop which, with the delay elements, during a calibrate mode, forms an adjustable oscillator and generates a sequence of signals the lapse of time between successive ones of which is established by delays imparted by selected ones of the delay elements. The delays imparted by selected ones of the delay elements. The output of the flip-flop is coupled to a shift register/counter which is used to measure the length of time required for the flip-flop to generate a prescribed number of signals after its receipt of an input signal. Upon counting a prescribed number of signals generated by the flip-flop the shift register/counter delivers an output signal to a comparator, which compares the length of time measured by the shift register/counter with a reference length of time. Depending upon the comparison, an up/down counter is incremented or decremented. Decoded contents of the counter are used to adjust the delay elements.