The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1989

Filed:

Jun. 01, 1984
Applicant:
Inventor:

Walter F Kosonocky, Skillman, NJ (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 24 ; 357 30 ;
Abstract

An infra-red charge-coupled device (IR-CCD) image sensor includes a substrate of single crystalline silicon having at one surface thereof a plurality of detectors arranged in space relation along a plurality of columns and a separate charge-coupled device (CCD) register extending along each column of detectors between the columns. Each CCD register includes a buried channel within the substrate and extending along and spaced from the detectors in the adjacent columns and at least two sets of gates extending completely across the space between the columns of detectors and crossing the buried channel. The gates are insulated from this substrate surface by a layer of silicon oxide. A first set of the gates are spaced apart along the column of detectors with each of the first gates having an extension extending over and insulated from the space between two adjacent detectors of one of the adjacent columns. A second set of gates are positioned between the first set of gates and each of the second gates has an extension extending over and insulated from the extension of one of the first gates. The gate extensions electrically connect corresponding gates of each of the CCD registers and extend to a terminal at an edge of the array. The gates of the CCD register form a surface barrier CCD with the portion of the substrate which is between the buried channel and the adjacent detectors which will prevent flow of charge from the detectors to the buried channel when the gates have a negative voltage applied thereto. The extensions of the first gates form a surface barrier CCD with the portion of the substrate between the detectors which will prevent flow of charge between adjacent detectors when the extensions have a negative voltage applied thereto. The surface channel CCD between each of the second gates and an adjacent detector will allow flow of charge from the adjacent detector to the buried channel when a positive voltage is applied to the second gate.


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