Control for three terminal power semiconductor devices

Abstract

A control circuit for generating gating signals to drive the SCRs of an AC switch coupled between a three phase AC source and a three phase load. A reference voltage signal is derived from the source and, after filtering, is applied to a squaring amplifier. The amplifier output is applied to a phase-locked loop (PLL). The output signal of the voltage controlled oscillator (VCO) of the PLL is fed back to the phase comparator thereof via two dividing counters. The output of one counter is applied to a logic block for generating a ramp reset signal in phase with a selected source phase-to-neutral voltage. The ramp reset signal is applied to a ramp forming circuit the output of which is applied to a first input of a comparator. The comparator receives a DC control voltage on its second input and provides on its output a gating signal corresponding to the source selected phase. Alternate pulses of that gating signal are separated to form two selected phase gating signals that are respectively applied as data inputs to two shift registers. The shift registers receive the VCO output as a clock signal and the remaining gating signals are provided, with appropriate phase delay, on the shift register outputs.