The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 1989
Filed:
Feb. 29, 1988
Jakob W Mulder, Eindhoven, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A sensor (CTD) which is formed with pick-up elements (D) for converting incident radiation (L) into electric charge packets which can be shifted to a sensor signal output (TO) through sensor elements under the control of clock pulse signals (CS1) may be beset with unwanted signal smear caused by the shifting process. To eliminate this, the relevant pick-up device includes a signal smear reduction circuit (SRC) which is specifically operative for a smear component produced during instantaneous shifting after a radiation information integration period. To this end, the signal smear reduction circuit (SRC) includes a signal subtraction circuit (SSC) which has an input (T1) coupled to the sensor signal output (TO), an output (T3) being coupled to an output (T4) of the pick-up device for the supply of an output signal with reduced signal smear and to an input (T5) of a series circuit (MEM, MUL, SC) comprising at least a summing memory device (MEM) and a signal attenuation circuit (MUL), whilst a series circuit output (T12) is coupled to another input (T2) of the signal subtraction circuit (SSC). A signal switching device (SC) which forms part of the series circuit (MEM, MUL, SC) of which is present between the sensor signal output (TO) and the input (T1) of the signal subtraction circuit (SSC) switches periodically on and off at a clock pulse frequency (1/CP) which is associated with the signal supply to the signal smear reduction circuit (SRC) and the summing memory device (MEM) has a reset (RS) which is operative before the signal supply to the signal smear reduction circuit (SRC) commences.