The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 1989

Filed:

Dec. 29, 1987
Applicant:
Inventors:

Hiroshi Itahana, Katsuta, JP;

Yoshinori Usui, Katsuta, JP;

Takashi Tsuboi, Katsuta, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 82 ; 357 76 ; 357 81 ;
Abstract

A semiconductor device is provided which includes first and second semiconductor elements of different types stacked alternately. A plurality of cooling members are each disposed between the paired first and second semiconductor elements located adjacent to each other for cooling the semiconductor elements and electrically connecting the elements to each other. In other words, the cooling members will have one of the first semiconductor elements on one side and one of the second semiconductor elements on the other side. At least one connecting conductor is provided for connecting at least one of the first semiconductor elements and at least one of the second semiconductor elements in an anti-parallel connection and also for connecting a plurality of the anti-parallel connections in series to one another. Because the first and second semiconductor elements are of different types from one another which are placed under a maximum load at different times, the cooling members will not be subjected to a maximum load on both sides at the same time. Therefore, the size of the cooling member can be decreased because it will only have to provide maximum cooling to one of the first and second semiconductor elements at a time.


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