Phase locked loop wherein phase comparing and filtering are performed by

Abstract

A phase-locked loop is formed by a series circuit of a counter, a register, an arithmetic unit, a low-pass filter, a PI-filter, and a voltage-controlled oscillator. The digital, internal clock signals generated by the oscillator are counted in a counter and are transferred into the register and stored as a current counter reading at points in time determined by time interval clock signals. For example, the time interval clock signals are acquired from reference clock signals by means of a divider and exhibit a lower frequency than the internal clock signals. A drive signal in digital form is determined in the arithmetic unit on the basis of the current counter reading, on the counter reading of the preceding evaluation interval, and on a rated value. This drive signal proceeds via a digital low-pass filter, PI-filter, and D/A converter to the control input of the oscillator, and controls the latter such that the internal clock signals coincide in phase with the reference clock signals.