Ecl to cmos transition amplifier

Abstract

When processing logic signals in ECL and CMOS circuitry it is necessary to adjust the logic levels when going from one type of circuitry to another. A problem which occurs is that smearing of a logic level occurs due to poor rise and fall times in a level adjusting amplifier. The rise and fall times can be improved by the level adjusting amplifier load circuit comprising the series connection of the source-drain paths of first and second N-channel transistors (20, 22), the parasitic capacitance of the drain of the first transistor (20) at a node (23), and by connecting the gate of the second transistor (22) to the node. In operation, when the first transistor (20) is non-conductive and the node (23) is charged, the second transistor (22) is operating in the triode or linear region of its characteristic in spite of its gate being at the voltage of the node. When the first transistor (20) is rendered conductive then both transistors (20, 22) are fully conductive and the starting discharge current is high. An amplifier including a symmetrical load is disclosed in FIG. 4.