Supervision circuit for a non-encoded binary bit stream

Abstract

An error supervision circuit for a non-encoded binary bit stream running through an elastic store comprising a memory having n locations, the bit rate of the stream supplied to the input of the memory differing from the bit rate of the stream produced at the output thereof. The successive bits in each group of n bits of the input stream are respectively written into the respective memory locations by write clock pulses supplied by a write register, at the input rate, and are successively read out from such locations by read clock pulses supplied by a read register at the output rate. The higher rate register is periodically interrupted for one or more bit periods to equalize filling and emptying of the memory. The bit streams at the input and output of the memory are supplied to respective data inputs of a comparator. A clock output of the lower rate register is connected to a first control input of the comparator to intermittently open a time window therein for receiving n bits of the lower rate bit stream. The corresponding clock output of the higher rate register is connected to a second control input of the comparator to intermittently open another time window therein for receiving n bits of the higher rate stream plus the number of bit periods during which the higher rate register has been interrupted. The comparator compares the bits in the two windows in regard to correspondence of the numbers of rising or falling edges or parity of the bits therein.