Hashing indexer for branch cache

Abstract

A Hashing Indexer For a Branch Cache for use in a pipelined digital processor that employs macro-instructions utilizing interpretation by micro-instructions. Each of the macro-instructions has an associated address and each of the micro instructions has an associated address. The hashing indexer includes a look-ahead-fetch system including a branch cache memory coupled to the prefetch section. An indexed table of branch target addressess each of which correspond to the address of a previously fetched instruction is stored in the branch cache memory. A predetermined number of bits representing the address of the macro-instruction being fetched is hashed with a predetermined number of bits representing the address of the micro-instruction being invoked. The indexer is used to apply the hashing result as an address to the branch memory in order to read out a unique predicted branch target address that is predictive of a branch for the hashed macro-instruction bits and micro-instruction bits. The hashing indexer disperses branch cache entries throughout the branch cache memory. Therefore, by hashing macro-instruction bits with micro-instruction bits and by dispersing the branch cache entries throughout the branch cache memory, the prediction rate of the system is increased.