The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 1989
Filed:
Jan. 28, 1988
Vikram Kowshik, San Jose, CA (US);
Elroy M Lucero, San Jose, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.