Fast recovery pnp loaded bipolar static ram memory cell with an

Abstract

A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarly, sense node (80) has associated therewith an NPN transistor (90) and a PNP load transistor (92) configured as an SCR. Each of these sense nodes is cross-coupled to the base of the NPN transistor connected to the opposite sense node. A forward biased PN junction is connected between an external Write circuit and the collector of each of the NPN transistors to provide an independent current path when changing from a low logic state to a high logic state. This decreases the recovery time when going from a saturated to a cut-off state for the NPN transistor. The PN junction can utilize either a forward bias collector of base junction of a PNP transistor or a series connected Schottky diode which has the cathode thereof connected to the sense node and the anode thereof connected to an external Write circuit. The memory cell is written to by providing a high voltage on one side of the PN junction and lowering the voltage on the emitters of the PNP load transistors such that current will flow through the PN junction.