The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 1989

Filed:

Apr. 19, 1985
Applicant:
Inventor:

Henry S Katzenstein, Pacific Palisades, CA (US);

Assignee:

Brooktree Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341148 ; 341145 ;
Abstract

Sub-sets of switches are provided each having a number of switches directly related to an individual bit in a binary coded input word. Signals representing the individual bits are introduced to the switches in the different sub-sets to obtain switch conductivities in accordance with such binary bits. The switches are connected in a repetitive array to provide paths through the conductive ones of the switches. The switches are connected to output members and a line to introduce the current through the output members to the line in accordance with the pattern of switch conductivities. This provides for progressive increases in the number of the output members connected to the line, ad for a continued connection to the line of output members previously connected to the line, with progressive increases in the binary value. The cumulative current through the line is indicative of the analog value. Additional circuitry may provide an indication of the reduced binary values relative to the binary values represented by the switches. An interpolation line may be connected to the repetitive array to receive a current from the output member to be connected next to the line for increasing binary values. The interpolation line and the additional circuitry may be connected to provide a current from such circuitry in accordance with the reduced binary values and to introduce such current to the line to provide an output current on the line in representation of the analog value. The additional circuitry may constitute another repetitive array.


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