Programming logic device with test-signal enabled output

Abstract

A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device. In a still further form, the AND plane further includes a plurality of test input lines each associated with the corresponding one of the product term lines of the AND plane, and an three-state output buffer is connected between the OR plane and a device output terminal, whereby the output buffer is enabled by a logical sum between a selected product term from the AND plane and an internally supplied test mode signal.