Bias current compensation for bipolar input stages

Abstract

The invention provides a circuit which substantially cancels the input bias current of an operational amplifier having a cascoded NPN-PNP inmput stage. The compensation circuit comprises three transistors. A first NPN transistor is coupled to the input stage such that its collector is coupled to the positive voltage source of the operational amplifier and its emitter is coupled to the emitter of the dual-collector transistor of the input stage. The second transistor, a PNP transistor, has its base coupled to the base of the dual-collector transistor and its collector coupled to the bases of both of the NPN transistors of the input stage, which form the inputs of the operational amplifier. This PNP transistor's emitter is coupled to the collector of a third transistor which is a dual-collector PNP transistor. A third transistor has an emitter coupled to the positive voltage source of the operational amplifier and a base coupled to the base of the NPN transistor of the compensation circuitry. The areas of the two collector regions of the dual collector PNP transistor are ratioed 2:1. This arrangement of three transistors provides a current to the bases of the input transistors substantially equal to the bias current they require; so virtually no external bias current is drawn from the input signals.