Sense amplifier for high performance dram

Abstract

A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines. A power-supply level voltage is supplied under the control of first and second control clock signals and boosted to a higher level charging voltage under the control of a third control clock signal, whereby the storage capacitors of the memory cells are charged to the higher voltage.