Multiple input clock selector

Abstract

A multiple input clock selector is provided for switching asynchronously from one to another of a plurality of oscillators that generate clock signals having different frequencies. The clock selector has a plurality of sections corresponding to the plurality of oscillators. Each section of the clock selector comprises an initial AND gate, a pair of flip-flops, and a final AND gate all connected in series. The oscillator signal for each section is applied to the final AND gate and to the flip-flops as a clock input. An inverted signal from the second flip-flop of each section is fed back as an input to the initial AND gates of all the other sections. An oscillator select signal is also provided as an input to the initial AND gate of each section. The outputs of all the final AND gates pass through an OR gate that provides the selected clock output. The clock selector switches between oscillators as determined by the select signals without producing runt pulses, metastable conditions, or other anomalous signals.