The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 1989
Filed:
Jun. 10, 1987
Applicant:
Inventor:
Roger J Gravrok, Minneapolis, MN (US);
Assignee:
Regents of the University of Minnesota, St. Paul, MN (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H01L / ;
U.S. Cl.
CPC ...
307443 ; 307448 ; 307450 ; 307475 ; 307542 ; 307558 ; 307574 ; 307581 ; 357 22 ;
Abstract
A new family of memory cells and digital-logic gates use an enhancement-mode driver, a voltage-level shifter, and a current regulator to provide improved noise margins and large logic swings. The voltage-level shifter and the current regulator are connected in series between an input and the control electrode of the driver. The voltage-level shifter establishes a voltage drop which is independent of current, while the current regulator establishes a constant current in the series path to the control electrode which is independent of voltage. The driver is an enhancement-mode device, such as a JFET, MESFET, or BJT.