The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 1989
Filed:
Jun. 11, 1987
Harold F Christensen, Saratoga, CA (US);
Jeffrey A Thomas, Cupertino, CA (US);
Jeffrey Isozaki, San Jose, CA (US);
Joseph A Petolino, Palo Alto, CA (US);
Amdahl Corporation, Sunnyvale, CA (US);
Abstract
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.