The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 1989
Filed:
Jan. 21, 1988
Naoyuki Kai, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor memory device includes a column decoder which is constructed such that it selects two adjacent columns in a memory cell array, and by means of which one of the two columns at a higher or lower position is selected, depending on whether or not a control signal indicates that one is added to a designated address. When the designated column address is the most significant address, the most and least significant addresses are selected, and if, in this case, the control signal indicates that one is added to the designated address, the least significant column address is selected and an address carry signal is generated. If, on the other hand, the control signal indicates that one is not added to the designated address, then the most significant column address is selected, in which case no address carry signal is generated. Similarly, a row decoder is constructed such that it selects two adjacent rows in the memory cell array, and one of the two columns at a higher or lower position is respectively selected, depending on whether or not an address carry signal is generated from the column decoder. When the designated row address is the most significant address, the most and least significant addresses are selected, and if, in this case, the address carry signal is generated from the column decoder, the least significant row address is selected, while if the address carry signal is not generated, then the most significant row address is selected.