Single plane dynamic decoder

Abstract

A single plane dynamic decoder wherein a typical decoder row comprises a P-channel transistor connected between a positive supply and a first node, a second N-channel transistor connected between ground potential and a second node, and a plurality of series-connected devices connected between the first node and the second node. The gates of the intermediate N-channel devices are connected to a corresponding input signal such that the intermediate devices are enabled or disabled depending on the state of the associated input. The gate of the P-channel device is connected to a clock signal such that it is enabled by a first clock phase and disabled by a second clock phase. The N-channel device is connected to the clock signal such that it is enabled by the second clock phase and disabled by the first clock phase. Thus, the first node is precharged when the P-channel device is enabled. This precharge activity occurs serially and hierarchically down the row depending on the state of the respective input signals. When the clock state changes, the N-channel device is enabled and the second node is discharged. The discharging of nodes will propagate serially up the row depending upon the state of the input signals. Therefore, the intermediate devices provide a NAND function. If each of the first nodes of adjacent rows are connected to a single output node, a wired-OR function results. Thus, a multi-term single plane dynamic decoder is provided that has the same functionality as a conventional two-plane AND-OR functional array or a static logic array.