Semiconductor integrated circuit with input protection circuit

Abstract

A semiconductor device having an input protection circuit is disclosed. The semiconductor device includes a power-on reset circuit which generates a pulse having a pulse width determined according to an input surge, applied to an input terminal when an input voltage has risen to a preset level. In response to a pulse generated by the power-on reset circuit, a CMOS inverter supplies a predetermined voltage to the base of a bipolar transistor and controls the bipolar transistor so that it clamps an input voltage supplied thereto to a voltage level lower than the withstanding voltage of the internal circuit in a period corresponding to the pulse width. Thus, the input protection circuit constituted by the bipolar transistor clamps an input voltage, supplied by the input terminal to the internal circuit, to a predetermined level. In this invention, the control circuit activates the bipolar transistor at the time the input voltage rises and keeps it active while the power-on reset circuit is generating a pulse, causing an input surge to be bypassed through the bipolar transistor, during this period of time. Thus, the input voltage can be clamped to a level lower than the withstanding voltage of the internal circuit, protecting the internal circuit, even when a surge voltage higher than the withstanding voltage is generated.