The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 1989
Filed:
Jun. 08, 1988
Roger W Fuller, Scotts Valley, CA (US);
David Bingham, San Jose, CA (US);
Maxim Integrated Products, Sunnyvale, CA (US);
Abstract
The invention relates to an output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply. The output circuit of the invention includes two terminals adapted to be connected to a power supply capable of providing a supply voltage. The output circuit includes an MOS transistor having a substrate, source and drain terminals and a gate, one of the source and drain terminals being coupled to one of the power supply terminals. A second transistor has three terminals including a control terminal and two other terminals, one of which is coupled to the other of the source and drain terminals of the MOS transistor, and the other of which is coupled to the other power supply terminal. An output terminal is coupled between the one terminal of the second transistor and the other of the source and drain terminals of the MOS transistor. A means responsive to an external signal is provided for rendering the output terminal in a high impedance state. A substrate control circuit coupled to the substrate, source and drain terminals of the MOS transistor has a means (1) for detecting whether the voltage at the output terminal is within the voltage range of the power supply, and (2) for controlling the voltage on the substrate of the MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased, while at the same time providing a voltage capable of disabling both the bipolar and the MOS transistors upon receipt of the external signal. This circuit, unlike prior art circuits, allows the output terminal to be driven significantly beyond the limits of the voltages at the terminals of the power supply, thus permitting its use in 'wired-or' configurations which are important where line driver outputs are used, allowing operation with multiple power supplies having differing voltages, or with no power supply at all.