The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 1989

Filed:

Jan. 22, 1988
Applicant:
Inventors:

William R Krenik, Dallas, TX (US);

Wei-Chan Hsu, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365203 ; 365190 ; 365205 ; 307530 ;
Abstract

A data latch with substantially zero hold time and with immunity to input data changes occurring after the latch has slewed toward a definable logic state. An input data flip-flop (10) is coupled via transfer transistors (40, 42) to an output data flip-flop (12). Output nodes (36,38) of the output data flip-flop (12) are prechargeable. Inhibit transistors (24,30) are cross-coupled between the input data flip-flop (10) and the output data flip-flop (12) to prevent input data changes from affecting the latch once the output data flip-flop (12) slews toward a definable stable state.


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Krenik, William. (1989). High-speed data latch with zero data hold time (U.S. Patent No. 4845675). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4845675

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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