Digital data multiple conversion system for converting data having a

Abstract

A digital data multiple conversion system which can be used in a digital data communication network and recover lost clock pulses. The system includes a memory unit storing input data having N bits, a first frequency divider frequency-dividing an input clock having a first frequency at N to output a first frequency-divided signal, a first pulse width expansion circuit connected to receive m frequency divided pulses from the first frequency divider, where m indicates the number of lost pulses of the input clock plus one receiving the input clock, and outputting a first pulse width expanded signal of the input clock having an m+1 pulse width, a circuit outputting a read clock having a second frequency near to the the first frequency and stuffing the read clock, a second frequency divider frequency-dividing the read clock at N to output a second frequency-divided signal, a second pulse width expansion circuit connected to receive n frequency divided pulses from the second frequency divider, where n indicates the number of lost pulses of the read clock plus one, receiving the read clock, and outputting a second width expanded signal of the read clock having an n+1 pulse width; a phase detector outputting a phase detection signal when the phases of both pulse width expanded signals coincide, and a stuffing request circuit outputting a stuffing request signal to the stuffing circuit. The stuffing circuit stuffs the read clock in response to the stuffing request signal.