The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 1989
Filed:
Feb. 25, 1986
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit device comprising a logic circuit which is constituted by using tri-state IIL gates. The tri-state IIL gates are particularly arranged to have first and second inputs. If the second input has a first level, the circuit will operate as a normal IIL circuit to provide high and low outputs in response to the first input. However, if the second input has a second level, the circuit will provide a floating output regardless of the first input. The transistors of the IIL circuit can be formed in an island in the substrate, with the potential of the island serving as the second input. In a preferred arrangement, the first level of the second input can be obtained by grounding the island while the second level is obtained by disconnecting the island from ground. These tri-state IIL gates are particularly advantageous to form a transfer gate for an IIL memory similar to the transfer gates used for MOS memories. They can also be used for forming various other logic gate arrangements.