The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 1989

Filed:

Oct. 14, 1987
Applicant:
Inventors:

David Nierescher, Renton, WA (US);

Douglas Yip, Bellevue, WA (US);

Assignee:

Data I/O Corporation, Redmond, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R / ;
U.S. Cl.
CPC ...
439331 ;
Abstract

A zero insertion force socket for integrated circuits having a contact pattern formed on the upper surface of a resilient circuit on which an integrated circuit is adapted to be placed with its leads in contact with the contact pattern. A plurality of frames having different sized cutouts conforming to the shape of integrated circuit cases of different sizes are used to position integrated circuits having cases of different sizes at predetermined locations on the contact pattern. The positioning frames are pivotally mounted on a common pin, and they nest together so that at least some of the positioning frames fit within the rectangular cutout of the next larger positioning frame. In order to bias the integrated circuit into the resilient circuit, a lid having a plunger is positioned over the integrated circuit. The plunder contacts the upper surface of the integrated circuit case to force it against the resilient circuit either with a constant force or a constant displacement. The plunger may project through the lid when it is displaced by an integrated circuit in order to indicate that an integrated circuit is installed in said socket.


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